The present application generally relates to the manufacture of integrated circuits and to lithographic methods for manufacturing integrated circuit on a wafer. More particularly, the present invention relates to the design and manufacture of lithographic masks for the manufacture of integrated circuits and a method for optimizing the mask design for manufacturability.
Integrated circuits are typically fabricated by optical lithographic techniques, where energy beams transmit integrated circuit images or patterns on photomasks (equivalently, masks or reticles) to photosensitive resists on semiconductor wafer substrates, formed (equivalently, printed or transferred) as multiple layers of patterned materials overlaid on the substrate. For each patterned layer formed on the substrate, there may be one or more masks used to form the printed patterns on the wafer. The patterns are typically expressed as polygons on the masks. However, the polygons of the mask transferred to or imaged on the wafer will be smoothed and distorted during the lithographic process of transferring the mask patterns to the wafer, due to a variety of optical effects, as is well-known in the art. Thus, it is desirable that the circuit designers take into account the characteristics of the lithographic process, as well as functional and performance requirements while designing the circuit layout.